A hardware architecture for dynamic performance and energy adaptation

A hardware architecture for dynamic performance and energy adaptation | Proceedings of the 2nd international conference on Power-aware computer systems

ACM Digital Library homePhillip Stanley-Marbell Dept. of ECE, Carnegie Mellon University, Pittsburgh, PA

Abstract

This paper proposes an architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache". The HBTC cache attempts to detect and omit unnecessary tag checks at run time. Execution footprints are recorded in an extended BTB (Branch Target Buffer), and are used to know the cache residence of target instructions before starting cache access. In our simulation, it is observed that our approach can reduce the total count of tag checks by 90%, resulting in 15% of cache-energy reduction, with less than 0.5% performance degradation.

Cite as:

Phillip Stanley-Marbell, Michael S. Hsiao, and Ulrich Kremer. 2002. A hardware architecture for dynamic performance and energy adaptation. In Proceedings of the 2nd international conference on Power-aware computer systems (PACS'02). Springer-Verlag, Berlin, Heidelberg, 33–52.

BibTeX:

@inproceedings{10.5555/1766991.1766995,
    author = {Stanley-Marbell, Phillip and Hsiao, Michael S. and Kremer, Ulrich},
    title = {A Hardware Architecture for Dynamic Performance and Energy Adaptation},
    year = {2002},
    isbn = {3540010289},
    publisher = {Springer-Verlag},
    address = {Berlin, Heidelberg},
    booktitle = {Proceedings of the 2nd International Conference on Power-Aware Computer Systems},
    pages = {33–52},
    numpages = {20},
    location = {Cambridge, MA, USA},
    series = {PACS'02}
}