Hardware and Compiler Techniques for Microprocessor Energy Reduction

Hardware and Compiler Techniques for Microprocessor Energy Reduction
Phillip Stanley-Marbell, Master Thesis, Rutgers University, 2001.


Reduction of the overall energy usage and per-cycle power consumption in microprocessors is becoming increasingly important as the level of device integration increases, increasing the energy density of generated heat, and creating problems in reliability, packaging, and overall energy usage. It is necessary to address energy efficiency both from the context of hardware, in the form of low power circuit, logic and microarchitectural designs, and from the context of software, in the form of energy effiient software, software that can take advantage of low power hardware features, and compiler and operating system support for energy efficiency. Presented are an infrastructure for investigating energy efficient hardware and software architectures, a hardware microarchitecture, and a compiler that permits software to take advantage of new trends in hardware architectures such as dynamic voltage and frequency scaling.
The infrastructure takes the form of a fast, flexible, cycle-accurate power estimating architectural simulator, that models a commercial microprocessor family. The simulator is shown to provide an order of magnitude speedup in simulation and energy estimation, over a contemporary state-of-the-art power estimating architectural simulator, while providing estimates within 10% of measurements from hardware.
The hardware architecture detects regions of application execution at runtime for which there is the possibility to run a device at a lower performance level, be reducing the operating frequency and/or operating voltage, incurring a degradation in performance, while saving energy. The proposed architecture, the Power Adaption Unit (PAU) may be used to control the operating voltage of system components, ranging from the CPU core, to memory and peripherals. An evaluation of the tradeoffs in performance versus energy saving of the PAU architecture is presented, along with results on its eefficacy on a specific hardware platform, for a set of SPEC CPU 200 integer and floating point benchmarks. It is shown that the PAU can provide energy savings of up to 18%, with overall performance degradation as low as 1%.
The presented compiler instruments C programs with mismatches in the amount of computation and memory references, to take advantage of facilities for dynamic voltage scaling and clock speed setting. The compiler is shown to provide up to 73% reduction in energy consumption.

Cite as:

P. Stanley-Marbell. Hardware and Compiler Techniques for Microprocessor Energy Reduction. Master thesis, Rutgers University, 2001.


  title={Hardware and Compiler Techniques for Microprocessor Energy Reduction},
  author={Stanley-Marbell, Phillip},
  school={Rutgers, The State University of New Jersey},